Barrier height voltage reference

ABSTRACT

A barrier height voltage reference includes two field-effect transistors which are substantially identical except for their gate-to-channel potential barrier characteristics and which are biased to carry equal drain currents at equal drain voltages. The resulting difference in potential between the gate contacts of the two field effect transistors produces a voltage reference which is substantially independent of operating point, supply potential, and temperature.

CROSS REFERENCE TO RELATED APPLICATION

This is a division of application Ser. No. 674,453, filed Apr. 7, 1976,now U.S. Pat. No. 4,068,134, said application Ser. No. 674,453 being acontinuation-in-part of a copending U.S. patent application Ser. No.587,188 filed June 16, 1975, now U.S. Pat. No. 3,975,648.

BACKGROUND AND SUMMARY OF THE INVENTION

Typical solid-state voltage reference devices generally obtain areference voltage from a predictable breakdown voltage or from a knownforward biased current-voltage relationship of a junction device.Temperature dependence of one device is often compensated for bycombination with another device also having a temperature dependence. Aconstant-current source is usually required for the best precision. Thepresent invention is a voltage reference comprising a pair offield-effect devices each substantially identical to the other exceptfor gate-to-channel potential barrier characteristics. Each field-effectdevice is biased with a substantially identical drain current to producea reference voltage corresponding to the difference in barrierpotentials at the gate-to-channel interface of the two field-effectdevices. The invention provides a voltage reference which issubstantially independent of operating point, supply potential, andtemperature.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional drawing of a junction field-effecttransistor.

FIGS. 2A-2C show energy band diagrams of two substantially identicalsemiconductor substrates wherein the first has in combination therewith,a metal gate of a first type and the second substrate has in combinationtherewith, a metal gate of a second type.

FIGS. 3A-3C show energy band diagrams of two semiconductor substrateshaving gates of the same material as the substrates, the gates beingdoped with different concentrations and forming P-N junctions with theirrespective substrates.

FIGS. 4A-4C show energy band diagrams of a first semiconductor substrateof a first type and a second semiconductor substrate substantiallyidentical to the first semiconductor substrate, the first semiconductorsubstrate having a semiconductor gate of a second type and the secondsemiconductor substrate having a semiconductor gate of a third type.

FIG. 5 is a diagram of a voltage reference made in accordance with theinvention.

FIGS. 6A-6D are a diagram illustrating the processing steps forfabricating a voltage reference monolithically in accordance with oneembodiment of the invention.

FIG. 7 is a diagram of another voltage reference made in accordance withthe invention.

FIG. 8 is a diagram showing a method for combining a plurality ofvoltage references made in accordance with the invention to achievelarger reference voltages.

FIG. 9 shows a preferred voltage reference wherein surface area requiredfor integrated fabrication is minimized.

FIG. 10 is a diagram of a preferred embodiment utilizing voltagevariable capacitors in accordance with the invention.

FIG. 11 is a diagram of another preferred embodiment utilizing voltagevariable capacitors.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The electrical characteristics of an N-channel field effect transistor,FET hereafter, operated above turn-on and below pinch-off are described,for example by A. S. Grove, Physics and Technology of SemiconductorDevices, John Wiley and Sons, Inc., New York, 1967: ##EQU1## where I_(D)is the drain current, Z is the channel width, q is the magnitude of theelectronic charge, μ_(n) is the electron mobility, N_(D) is the densityof donors in the channel region, d is the channel thickness, L is thechannel length, V_(D) is the drain voltage which is measured between thedrain and the source, ε₂ is the semiconductor dielectric constant, φ_(B)is the built-in potential between the gate and the channel and referredto herein as the barrier potential, and V_(G) is the gate voltage whichis measured between the gate and the source.

A FET operated in the pinch-off condition is also described by Equation1 wherein the value for V_(D) is constant and V_(D) is given by (see,for example, Physics and Technology of Semiconductor Devices as citedabove): ##EQU2##

Equations 1 and 2 are applicable to a junction FET having geometrysimilar to that of FIG. 1. Equations similar to equations 1 and 2 arealso applicable to metal gate FETs as well as to heterojunction FETs.

For two FETs, identical except for their gate-to-channel potentials andbiased with equal I_(D) 's in pinch-off or equal I_(D) 's and V_(D) 'sbelow pinch-off, the quantity (φ_(B) -V_(G)) is identical. A referencevoltage can therefore be developed, which is:

    V.sub.Ref =ΔV.sub.G =Δφ.sub.B              Equ. 3

where V_(Ref) is the reference voltage, ΔV_(G) is the difference in gatevoltages, and αφ_(B) is the difference in barrier potentials. Thisreference voltage is developed whether or not the FET's are operatedabove or below pinch-off. It is also developed when the FET's areoperated below turn-on so long as identical I_(D) 's and V_(D) 's aremaintained.

Referring to FIG. 1, there is shown an FET having an n-channel 802connected to a back gate 804 of p-type semiconductor material, a frontgate 806 also of p-type semiconductor material, a source contact 808,and a drain contact 810. While FIG. 1 shows a junction FET having both atop gate 806 and a back gate 804 wherein both form step homojunctions,the only requirement for making a voltage reference in accordance withthis invention is that two FET's be substantially identical except forthe gate-to-channel built-in potential of at least one gate-to-channeljunction.

A difference in φ_(B) 's is obtained, for example, by utilizing twodifferent metals for gates which make rectifying contacts to thesubstrates but which result in different gate-to-channel built-inpotentials. FIG. 2(a) shows the energy band diagrams of twosubstantially identical semiconductor substrates 402 and 404 which are,for example, n-type, the first semiconductor substrate 402 beingconnected to a first gate metal 406, and the second semiconductorsubstrate 404 being connected to a second gate metal 408. Gate metals406 and 408 are chosen so as to make rectifying contact with thesemiconductor substrates 402 and 404 and so that the barrier potentialφ_(B1) of the first FET is greater than the barrier potential φ_(B2) ofthe second FET. Since φ_(B2) is smaller than φ_(B1), the channel widthis larger in the second semiconductor substrate 404 than in the firstsemiconductor substrate 402. As shown in FIG. 2(b) biasing the secondgate metal 408 with respect to the second semiconductor substrate 404 byan amount φ_(B2) -φ_(B1) results in the channel width of the secondsemiconductor substrate 404 being the same as in the first semiconductorsubstrate 402. A reference voltage V_(Ref) =φ_(B2) -φ_(B1) is therebyproduced. In FIG. 2(c) gate metals 406 and 408 are biased by differentvoltages from those shown in FIG. 2(b). However, the channel width inthe second semiconductor substrate 404 is the same as in the firstsemiconductor substrate 402, resulting in the same reference voltage(V_(Ref) =φ_(B2) -φ_(B1)) as in FIG. 2(b).

The difference in φ_(B) 's is also obtained by utilizing twosemiconductor materials for the gates which are the same as thesemiconductor material of the two substrates and utilizing a first gatesemiconductor material which has a first doping density different fromthe doping density of the second gate semiconductor material. FIG. 3(a)illustrates an energy band diagram for two substantially identicalsemiconductor substrates 502 and 504. The first semiconductor substrate502 is connected to a first semiconductor gate 506, and the secondsemiconductor substrate 504 is connected to a second semiconductor gate508. The doping species of semiconductor gates 506 and 508 are chosen sothat the majority carrier of the semiconductor substrates 502 and 504 isof different polarity from that of the semiconductor gates 506 and 508.The magnitude of the doping density in the first semiconductor gate 506is different from that of the second semiconductor gate 508 therebyproducing different gate-to-channel built-in potentials. Since φ_(B2) issmaller than φ_(B1), the channel width is larger in the secondsemiconductor substrate 504 than in the first semiconductor substrate502. As shown in FIG. 3(b), biasing the second semiconductor gate 508with respect to the second semiconductor substrate 504 by an amountφ_(B2) -φ_(B1) results in the channel width of the second semiconductorsubstrate 504 being the same as in the first semiconductor substrate502. A reference voltage (V_(Ref) =φ_(B2) -φ_(B1)) is thereby produced.In FIG. 3(c) semiconductor gates 506 and 508 are biased by differentvoltages from those shown in FIG. 3(b). However, the channel width insemiconductor substrate 504 is also the same as in semiconductorsubstrate 502, resulting in the same reference voltage (V_(Ref) =φ_(B2)-φ_(Bl)) as in FIG. 3(b).

The difference in φ_(B) 's is also obtained by utilizing two differentsemiconductor materials for the gates. FIG. 4(a) shows two substantiallyidentical semiconductor substrates 602 and 604 which are of a firstsemiconductor material which is, for example, n-type. The firstsemiconductor substrate 602 is connected to a first semiconductor gate606, which is of a second semiconductor material and which is, forexample, p-type. The second semiconductor substrate 604 is connected toa second semiconductor gate 608 which is of a third semiconductormaterial and which is, for example, p-type. The materials and dopingspecies of semiconductor gates 606 and 608 are chosen so that rectifyingcontact is made to the semiconductor substrates 602 and 604 and so thatφ_(B1) is not equal to φ_(B2). Since φ_(B2) is smaller than φ_(B1), thechannel width is larger in the second semiconductor substrate 604 thanin the first semiconductor substrate 602. Biasing the secondsemiconductor gate 608 with respect to the second semiconductorsubstrate 604, as shown in FIG. 4(b) by the amount φ_(B2) -φ_(B1)results in the channel width of the second semiconductor substrate 604being the same as in the first semiconductor substrate 602. A referencevoltage V_(Ref) =φ_(B2) -φ_(B1) is thereby produced between the secondsemiconductor gate 608 and the first semiconductor gate 606. In FIG.4(c) semiconductor gates 606 and 608 are biased by different voltagesfrom those shown in FIG. 4(b). However, the channel width in the firstsemiconductor substrate 602 is also the same as in the secondsemiconductor substrate 604, resulting in the same reference voltage(V_(Ref) =φ_(B2) -φ_(B1)) as in FIG. 4(b).

Combinations of gate materials shown in FIGS. 2-4 can also be used tofabricate a voltage reference in accordance with this invention. Suchvoltage references include the following combinations: (1) ahomojunction and a schottky barrier, (2) a homojunction and aheterojunction, and (3) a schottky barrier and a heterojunction.

Referring to FIG. 5, there is shown a first preferred embodiment made inaccordance with the invention. A first n-channel FET 5 and a secondn-channel FET 7 are substantially identical except for different barrierpotentials. A bias supply 1 is connected between source contact 13 anddrain contact 17 of FET 5 and a bias supply 3 is connected betweensource contact 15 and drain contact 19 of FET 7. The potentials of gatecontact 35 of FET 5 and gate contact 37 of FET 7 are adjusted by gatebiasing means not shown in FIG. 5. The gate biasing means not shown inFIG. 5, the supply source 1 and the supply source 3 are adjusted so thatthe drain voltage of FET 5 is substantially equal to the drain voltageof FET 7 and the drain current of FET 5 is substantially equal to thedrain current of FET 7. A reference voltage, V_(Ref), is produced by thedifference between the potentials of the gate contact 35 of FET 5 andthe gate contact 37 of FET 7.

The matching of the two FET's is enhanced by fabricating them in closeproximity to each other on the same substrate. The substrate dopingdensities and the mobilities are then substantially the same in bothFET's. FIG. 6 shows processing steps to fabricate monolithically twoschottky barrier FET's which are identical except for their gate metals.Referring to FIG. 6(a), a high resistivity substrate 702, such as, forexample, silicon, is first cleaned and polished. A low resistivityepitaxial layer 704 is then grown on the substrate 702. The field oxide706 is grown, and the isolation diffusion windows 708 opened, followedby the isolation diffusion 710. As shown by FIG. 6(b), source and drainwindows 712 and 714 are etched, followed by source and drain diffusions716 and 718. In FIG. 6(c) gate window 720 and source and drain contacts722 and 724 are etched, followed by deposition of a first metal 725, as,for example, by RF sputtering platinum. The first metal is removedexcept over the source and drain contacts 722 and 724 and over gatewindow 720. Referring to FIG. 6(d), second gate window 726 is etched anda second metal 727 is deposited, as, for example, by electron-beamevaporating titanium. The second metal 727 is removed everywhere exceptover the previously deposited first metal 725, except for any necessaryinterconnecting metal and bonding pads, and except over the second gatewindow 726. Modifications to the above processing steps are possible.One such modification, for example, is to fabricate the two FET's eitheron the same or different substrates using the same processing stepsuntil after the contact mask step. The FET's are separated and differentgate field plate metals and interconnecting metals are deposited oneach.

V_(Ref) is temparature dependent only to the extent of mismatches in theFET's and to the extent of the difference in temperarture coefficientsof their respective gate-to-channel barrier heights.

Referring to FIG. 7, there is shown another preferred embodiment made inaccordance with the invention. A first p-channel FET 2 and a secondp-channel FET 4 are substantially identical except for differentgate-to-channel barrier heights. An amplifier 6 is coupled to drive gate44 of FET 4. Amplifier 6 has a non-inverting input connected to sourcecontact 20 of FET 2 and a resistor 8 and an inverting input connected tosource contact 40 of FET 4 and a resistor 10. Amplifier 6 has a largerinput impedance as compared with the resistances of resistors 8 and 10.A negative supply voltage is coupled across terminal 12 and ground 14.Drain contacts 22 and 42 are connected to terminal 12. Gate contact 24of FET 2, resistor 8 and resistor 10 are connected to ground 14. Thedrain currents and drain voltages of FET 2 and FET 4 are maintainedsubstantially equal by selecting matching resistances 8 and 10 and bythe action of amplifier 6 driving the gate contact 44 of FET 4. Areference voltage is obtained across terminals 16 and 14.

Referring to FIG. 8, there is shown a combination comprising two of thevoltage references depicted in FIG. 7. The reference voltage is obtainedacross terminals 16 and 14. A plurality of references may be similarlycombined to provide larger reference voltages.

Referring to FIG. 9, matched FET's 28 and 30 are substituted for thematched resistors 8 and 10 in the embodiment depicted in FIG. 7. Thissubstitution allows conservation of substrate area should largeresistance values be required for the resistors R8 and R10.

Other φ_(B) dependent parameters, as, for example, the AC (alternatingcurrent) conductance and transconductance, of the FETs can also bedetected and used to adjust the bias conditions so that a referencevoltage is obtained.

The invention may also be fabricated using two voltage variablecapacitors. Gate-to-substrate junctions are made, as described above forthe FETs. Referring to FIG. 2, it is seen that the depletion layer insemiconductor substrate 404 is substantially the same as insemiconductor substrate 402 if gate 408 is biased with respect tosemiconductor 404 at a voltage V_(Ref) more negative than gate 406 isbiased with respect to semiconductor substrate 402. For such a biascondition the capacitance between gate 406 and substrate 402 will besubstantially equal to that between 408 and substrate 404. Thesemiconductor junctions of FIG. 3 and the heterojunctions of FIG. 4 mayalso be used so long as the major part of the depletion layer extendsinto the substrates.

Referring to FIG. 10, a preferred embodiment made in accordance with theinvention using voltage variable capacitors is shown. Voltages areapplied to each of two voltage variable capacitors so that the samedepletion layer width is obtained in each voltage variable capacitor,thereby resulting in the same capacitance for each capacitor. The twocapacitors are essentially identical except for their built-inpotential. A reference voltage V_(Ref) is produced, which is given by:

    |V.sub.Ref |=|V.sub.G1 -V.sub.G2 |=|φ.sub.B1 -φ.sub.B2 |Equ. 4

where V_(G1) and V_(G2) are gate-to-substrate voltages for first andsecond voltage-variable capacitors 202 and 204 and φ_(B1) and φ_(B2) arethe respective built-in potentials for the first and second voltagevariable capacitors 202 and 204. The gate-to-substrate voltages arevaried to obtain matching capacitances.

An alternating current (AC) voltage source 206 is coupled by couplingcapacitors 208 and 209 to gates 210 and 212 of the voltage variablecapacitors 202 and 204, respectively. Substrate contacts 214 and 216 ofthe voltage variable capacitors 202 and 204 are coupled to ground 200 byresistors 218 and 219, respectively. Resistors 218 and 219 are ofsubstantially identical resistance and are coupled respectively torectifiers and filters 220 and 222. Outputs 228 and 230 of therectifiers and filters 220 and 222 are coupled to differential inputs ofamplifier 224. The amplifier 224 has an output coupled to the gate 210of the voltage variable capacitor 202.

The resistance of resistors 218 and 219 is selected to be less then themagnitude of the reactance of voltage variable capacitors 202 and 204.Biasing means 226 adjusts the capacitance of voltage variable capacitor204 to a convenient value and biasing means 226 has an impedance ofmagnitude greater than the magnitude of the reactance of voltagevariable capacitor 204. The magnitudes of reactances of couplingcapacitors 208 and 209 are chosen to be less than the magnitude ofreactances a voltage variable capacitors 202 and 204 at the frequency ofAC voltage source 206.

Alternating current voltages having magnitudes substantiallyproportional to the capacitances of voltage variable capacitors 202 and204 are developed at substrate contacts 214 and 216. These voltages areconverted to direct current (DC) voltages by rectifiers and filters 220and 222 to produce signals at outputs 228 and 230 which drivedifferential amplifier 224. Amplifier 224 drives the voltage at the gate210 of voltage variable capacitor 202 until the capacitance of voltagevariable capacitor 202 is substantially equal to the capacitance ofvoltage variable capacitor 204. The reference voltage V_(Ref) isdeveloped between gate 210 and gate 212 and is substantially equal tothe difference in built-in potentials of field-effect capacitors 202 and204. p Referring to FIG. 11, there is shown another preferred embodimentmade in accordance with the invention. Identical AC current sources 305and 306 drive identical AC currents into voltage variable capacitors 302and 304 which are substantially identical except for their built-inpotentials. Rectifying and filtering means 320 and 322 are connected tovoltage variable capacitors 302 and 304 respectively.

A DC voltage is produced at input terminals 328 and 330 of amplifier 324which forces the output of amplifier 324 to bias voltage variablecapacitor 302 such that its capacitance is equal to that of voltagevariable capacitor 304. A reference voltage V_(Ref) is produced betweenterminals 350 and 352 which is equal to the difference in the built-inpotentials of voltage variable capacitors 302 and 304 (see Equation 4).Bias source 326 is adjusted to obtain a convenient value of capacitance.

Differences in voltage variable capacitor built-in potentials areproduced, for example, by the techniques disclosed herein with respectto field-effect transistors.

Given below are tables of approximate voltage reference values producedby the embodiments discussed hereinabove for various metal combinationson the substrate material types indicated. In general, the values givenbelow are processing dependent and are affected by the degree ofsubstrate doping as well as species. A V_(Ref) obtained in practise cantherefor vary from the V_(Ref) 's given below.

                  TABLE I                                                         ______________________________________                                        Substrate: n-type AlAs                                                                  Au           Pt                                                     ______________________________________                                        Au          --             0.2                                                Pt          --             --                                                 ______________________________________                                    

                  TABLE II                                                        ______________________________________                                        Substrate: n-CdS                                                              Pt        Au      Pd       Cu     Ag     Ni                                   ______________________________________                                        Pt    --      0.4     0.5    0.6    0.8    0.4                                Au    --      --       0.06  0.18   0.3    0.3                                Pd    --      --      --     0.12   0.2    0.2                                Cu    --      --      --     --      0.06   0.09                              Ag    --      --      --     --     --      0.11                              ______________________________________                                    

                  TABLE III                                                       ______________________________________                                        Substrate: n-type CdSe                                                        Pt           Au         Ag         Cu                                         ______________________________________                                        Pt     --        0.12       0.06     0.04                                     Au     --        --         0.06     0.16                                     Ag     --        --         --       0.10                                     ______________________________________                                    

                  TABLE IV                                                        ______________________________________                                        Substrate: n-type CdTe                                                        Au           Pt         Ag         Al                                         ______________________________________                                        Au     --        0.02       0.06     0.16                                     Pt     --        --         0.08     0.18                                     Ag     --        --         --       0.10                                     ______________________________________                                    

                  TABLE V                                                         ______________________________________                                        Substrate: n-type GaAs                                                        Au        Pt      Be       Ag     Cu     Al                                   ______________________________________                                        Au    --      0.04    0.09   0.02   0.08   0.10                               Pt    --      --      0.05   0.02   0.04   0.06                               Be    --      --      --     0.09   0.01   0.01                               Ag    --      --      --     --     0.06   0.08                               Cu    --      --      --     --     --     0.02                               ______________________________________                                    

                  TABLE VI                                                        ______________________________________                                        Substrate: p-type GaAs                                                                  Au           Al                                                     ______________________________________                                        Au          --             0.08                                               ______________________________________                                    

                  TABLE VII                                                       ______________________________________                                        Substrate: n-type GaP                                                         Cu        Al      Au       Pt     Mg     Ag                                   ______________________________________                                        Cu    --      0.15    0.08   0.2    0.16   --                                 Al    --      --      0.2    0.4    0.01   0.15                               Au    --      --      --      0.17  0.2    0.08                               Pt    --      --      --     --     0.4    0.2                                Mg    --      --      --     --     --     0.16                               ______________________________________                                    

                  TABLE VIII                                                      ______________________________________                                        Substrate: n-type Ge                                                                    Au           Al                                                     ______________________________________                                        Au          --             0.03                                               ______________________________________                                    

                  TABLE IX                                                        ______________________________________                                        Substrate: n-type InP                                                                   Au           Ag                                                     ______________________________________                                        Au          --             0.05                                               ______________________________________                                    

                  TABLE X                                                         ______________________________________                                        Substrate: n-type PbO                                                         Ag         Bi        Ni        Pb     In                                      ______________________________________                                        Ag    --       0.01      0.01    --     0.02                                  Bi    --       --        0.02    0.01   0.01                                  Ni    --       --        --      0.01   0.03                                  Pb    --       --        --      --     0.02                                  ______________________________________                                    

                  TABLE XI                                                        ______________________________________                                        Substrate: n-type Si                                                          Au           Mo         PtSi       W                                          ______________________________________                                        Au     --        0.2        0.07     0.13                                     Mo     --        --         0.3      0.09                                     PtSi   --        --         --       0.2                                      ______________________________________                                    

                  TABLE XII                                                       ______________________________________                                        Substrate: p-type Si                                                                    Au           PtSi                                                   ______________________________________                                        Au          --             0.05                                               ______________________________________                                    

                  TABLE XIII                                                      ______________________________________                                        Substrate: n-type SiC                                                                   Au           Al                                                     ______________________________________                                        Au          --             0.05                                               ______________________________________                                    

                  TABLE XIV                                                       ______________________________________                                        Substrate: n-type S.sub.n O.sub.2                                                    Au        Ag          Cu                                               ______________________________________                                        Au       --          0.3         0.5                                          Ag       --          --          0.18                                         ______________________________________                                    

                  TABLE XV                                                        ______________________________________                                        Substrate: n-type ZnO                                                         Au           Pt         Pd         Ag                                         ______________________________________                                        Au     --        0.10       0.03     0.03                                     Pt     --        --         0.07     0.07                                     ______________________________________                                    

                  TABLE XVI                                                       ______________________________________                                        Substrate: n-type ZnS                                                         Au      Pd      Pt     Cu   Ag   In   Al   Ti   Mg                            ______________________________________                                        Au   --     0.13    0.16 0.2  0.4  0.5  1.2  0.9  1.2                         Pd   --     --      0.03 0.12 0.2  0.4  1.1  0.8  1.0                         Pt          --      --   0.09 0.19 0.3  1.0  0.7  1.0                         Cu   --     --      --   --   0.10 0.2  1.0  0.6  0.9                         Ag   --     --      --   --   --    0.15                                                                              0.8  0.6  0.8                         In   --     --      --   --   --   --   0.7  0.4  0.7                         Al   --     --      --   --   --   --   --   0.3   0.02                       Ti   --     --      --   --   --   --   --   --   0.3                         ______________________________________                                    

                  TABLE XVII                                                      ______________________________________                                        Substrate: n-type ZnSe                                                        Au           Pt         Cu         Mg                                         ______________________________________                                        Au     --        0.04       0.26     0.7                                      Pt     --        --         0.3      0.7                                      Cu     --        --         --       0.4                                      ______________________________________                                    

                  TABLE XVIII                                                     ______________________________________                                        Substrate: n-type ZnO                                                                Cu        In          Ti                                               ______________________________________                                        Cu       --          0.15        0.15                                         In       --          --          --                                           ______________________________________                                    

We claim:
 1. A method of fabricating a voltage reference comprising thesteps of:growing an epitaxial layer on a substrate material havinghigher resistivity than that of the epitaxial layer; growing a fieldoxide layer on the epitaxial layer; opening a first isolation diffusionwindow, a second isolation diffusion window and a third isolationdiffusion window in the field oxide layer; forming isolation diffusionsin the low resistivity epitaxial layer within each of the first, secondand third isolation diffusion windows; etching a first source window, afirst drain window, a second source window and a second drain window inthe field oxide layer; forming source diffusions in the epitaxial layerwithin the first and second source windows and drain diffusions in theepitaxial layer within the first and second drain windows; etching afirst gate window in the field oxide layer; etching a first sourcecontact window, a first drain contact window, a second source contactwindow and a second drain contact window in the field oxide layer;depositing a first metal on the epitaxial layer through the first gatewindow, the first source contact window, the first drain contact window,the second source contact window and the second drain contact window;etching a second gate window in the field oxide layer; and depositing asecond metal through the first gate window, the first source contactwindow, the first drain contact window, the second source contactwindow, the second drain contact window and the second gate window, thesecond metal being different from said first metal.
 2. A method as inclaim 1 comprising the additional step after the step of forming sourceand drain diffusions in the epitaxial layer of separating thesemiconductor substrate into two parts, each part having one source andone drain diffusion.
 3. A method as in claim 1 wherein the step ofgrowing an epitaxial layer on a substrate material comprises the step ofgrowing an epitaxial layer on n-type AlAs and the steps of depositingfirst and second metals comprise the steps of depositing first andsecond metals selected from the group consisting of Au and Pt, the firstand second metals being different.
 4. A method as in claim 1 wherein thestep of growing an epitaxial layer on a substrate material comprises thestep of growing an epitaxial layer on n-type CdS and the steps ofdepositing first and second metals comprise the steps of depositingfirst and second metals selected from the group consisting of Pt, Au,Pd, Cu, Ag, and Ni, the first and second metals being different.
 5. Amethod as in claim 1 wherein the step of growing an epitaxial layer on asubstrate material comprises the step of growing an epitaxial layer onn-type CdSe and the steps of depositing first and second metals comprisethe steps of depositing first and second metals selected from the groupconsisting of Pt, Au, Ag, and Cu, the first and second metals beingdifferent.
 6. A method as in claim 1 wherein the step of growing anepitaxial layer on a substrate material comprises the step of growing anepitaxial layer on n-type CdTe and the steps of depositing first andsecond metals comprise the steps of depositing first and second metalsselected from the group consisting of Au, Pt, Ag, and Al, the first andsecond metals being different.
 7. A method as in claim 1 wherein thestep of growing an epitaxial layer on a substrate material comprises thestep of growing an epitaxial layer on n-type GaAs and the steps ofdepositing first and second metals comprise the steps of depositingfirst and second metals selected from the group consisting of Au, Pt,Be, Ag, Cu, and Al, the first and second metals being different.
 8. Amethod as in claim 1 wherein the step of growing an epitaxial layer on asubstrate material comprises the step of growing an epitaxial layer onp-type GaAs and the steps of depositing first and second metals comprisethe steps of depositing first and second metals selected from the groupconsisting of Au and Al, the first and second metals being different. 9.A method as in claim 1 wherein the step of growing an epitaxial layer ona substrate material comprises the step of growing an epitaxial layer onn-type GaP and the steps of depositing first and second metals comprisethe steps of depositing first and second metals selected from the groupconsisting of Cu, Al, Au, Pt, Mg and Ag, the first and second metalsbeing different.
 10. A method as in claim 1 wherein the step of growingan epitaxial layer on a substrate material comprises the step of growingan epitaxial layer on n-type Ge and the steps of depositing first andsecond metals comprise the steps of depositing first and second metalsselected from the group consisting of Au and Al, the first and secondmetals being different.
 11. A method as in claim 1 wherein the step ofgrowing an epitaxial layer on a substrate material comprises the step ofgrowing an epitaxial layer on n-type InP and the steps of depositingfirst and second metals comprise the steps of depositing first andsecond metals selected from the group consisting of Au and Ag, the firstand second metals being different.
 12. A method as in claim 1 whereinthe step of growing an epitaxial layer on a substrate material comprisesthe step of growing an epitaxial layer on n-type PbO and the steps ofdepositing first and second metals comprise the steps of depositingfirst and second metals selected from the group consisting of Ag, Bi,Ni, Pb, and In, the first and second metals being different.
 13. Amethod as in claim 1 wherein the step of growing an epitaxial layer on asubstrate material comprises the step of growing an epitaxial layer onn-type Si and the steps of depositing first and second metals comprisethe steps of depositing first and second metals selected from the groupconsisting of Au, Mo, PtSi and W the first and second metals beingdifferent.
 14. A method as in claim 1 wherein the step of growing anepitaxial layer on a substrate material comprises the step of growing anepitaxial layer on p-type Si and the steps of depositing first andsecond metals comprise the steps of depositing first and second metalsselected from the group consisting of Au and PtSi, the first and secondmetals being different.
 15. A method as in claim 1 wherein the step ofgrowing an epitaxial layer on a substrate material comprises the step ofgrowing an epitaxial layer on n-type SiC and the steps of depositingfirst and second metals comprise the steps of depositing first andsecond metals selected from the group consisting of Au and Al the firstand second metals being different.
 16. A method as in claim 1 whereinthe step of growing an epitaxial layer on a substrate material comprisesthe step of growing an epitaxial layer on n-type SnO2 and the steps ofdepositing first and second metals comprise the steps of depositingfirst and second metals selected from the group consisting of Au, Ag andCu, the first and second metals being different.
 17. A method as inclaim 1 wherein the step of growing an epitaxial layer on a substratematerial comprises the step of growing an epitaxial layer on n-type ZnOand the steps of depositing first and second metals comprise the stepsof depositing first and second metals selected from the group consistingof Au, Pt, Pd, and Ag, the first and second metals being different. 18.A method as in claim 1 wherein the step of growing an epitaxial layer ona substrate material comprises the step of growing an epitaxial layer onn-type ZnS and the steps of depositing first and second metals comprisethe steps of depositing first and second metals selected from the groupconsisting of Au, Pd, Pt, Cu, Ag, In, Al, Ti, and Mg, the first andsecond metals being different.
 19. A method as in claim 1 wherein thestep of growing an epitaxial layer on a substrate material comprises thestep of growing an epitaxial layer on n-type ZnSe and the steps ofdepositing first and second metals comprise the steps of depositingfirst and second metals selected from the group consisting of Au, Pt,Cu, and Mg the first and second metals being different.
 20. A method asin claim 1 wherein the step of growing an epitaxial layer on a substratematerial comprises the step of growing an epitaxial layer on n-type ZnOand the step of depositing a first metal comprises the step ofdepositing a metal selected from the group consisting of In and Ti andthe step of depositing a second metal comprises the step of depositingCu.
 21. A method as in claim 1 wherein the step of growing an epitaxiallayer on a substrate material comprises the step of growing an epitaxiallayer on a substrate material selected from the group consisting ofn-type AlAs, n-type CdS, n-type CdSe, n-type CdTe, n-type GaAs, p-typeGaAs, n-type GaP, n-type Ge, n-type InP, n-type PbO, n-type Si, p-typeSi, n-type SiC, n-type SnO₂, n-type ZnO, n-type ZnS, and n-type ZnSe.22. A method of fabricating a voltage reference comprising the stepsof:growing an epitaxial layer on a first substrate material havinghigher resistivity than that of the epitaxial layer; growing a fieldoxide layer on the epitaxial layer; opening an isolation diffusionwindow in the field oxide layer; forming isolation diffusion in theepitaxial layer within the isolation diffusion window; etching sourceand drain windows in the field oxide layer; forming source and draindiffusions in the epitaxial layer within the source and drain windows;etching a source contact window, a drain contact window and a gatewindow in the field oxide layer; depositing a first metal through theetched source contact window, the etched drain contact window and theetched gate window; growing a second epitaxial layer which issubstantially identical to the first epitaxial layer on a secondsubstrate material; growing a second field oxide layer on the secondepitaxial layer; opening a second isolation diffusion window in thesecond field oxide layer; forming isolation diffusions in the secondepitaxial layer within the second isolation diffusion window; etching asecond source window and a second drain window in the second field oxidelayer; forming source and drain diffusions in the second epitaxial layerwithin the second source window and the second drain window; etching asecond source contact window, a second drain contact window and a secondgate window in the second field oxide layer; and depositing a secondmetal through the etched second source contact window, second draincontact window and second gate window, the second metal being differentfrom the first metal.
 23. A method as in claim 22 wherein the step ofgrowing an epitaxial layer on a first substrate material comprises thestep of growing an epitaxial layer on n-type AlAs;the step of growing anepitaxial layer on a second substrate material comprises the step ofgrowing an epitaxial layer on n-type AlAs; and the steps of depositingfirst and second metals comprise the steps of depositing first andsecond metals selected from the group consisting of Au and Pt, the firstand second metals being different.
 24. A method as in claim 22 whereinthe step of growing an epitaxial layer on a first substrate materialcomprises the step of growing an epitaxial layer on n-type CdS;the stepof growing an epitaxial layer on a second substrate material comprisesthe step of growing an epitaxial layer on n-type CdS; and the steps ofdepositing first and second metals comprise the steps of depositingfirst and second metals selected from the group consisting of Pt, Au,Pd, Cu, Ag and Ni, the first and second metals being different.
 25. Amethod as in claim 22 wherein the step of growing an epitaxial layer ona first substrate material comprises the step of growing an epitaxiallayer on n-type CdSe;the step of growing an epitaxial layer on a secondsubstrate material comprises the step of growing an epitaxial layer onn-type CdSe; and the steps of depositing first and second metalscomprise the steps of depositing first and second metals selected fromthe group consisting of Pt, Au, Ag and Cu, the first and second metalsbeing different.
 26. A method as in claim 22 wherein the step of growingan epitaxial layer on a first substrate material comprises the step ofgrowing an epitaxial layer on n-type CdTe;the step of growing anepitaxial layer on a second substrate material comprises the step ofgrowing an epitaxial layer on n-type CdTe; and the steps of depositingfirst and second metals comprise the steps of depositing first andsecond metals selected from the group consisting of Au, Pt, Ag and Al,the first and second metals being different.
 27. A method as in claim 22wherein the step of growing an epitaxial layer on a first substratematerial comprises the step of growing an epitaxial layer on n-typeGaAs;the step of growing an epitaxial layer on a second substratematerial comprises the step of growing an epitaxial layer on n-typeGaAs; and the steps of depositing first and second metals comprise thesteps of depositing first and second metals selected from the groupconsisting of Au, Pt, Be, Ag, Cu and Al, the first and second metalsbeing different.
 28. A method as in claim 22 wherein the step of growingan epitaxial layer on a first substrate material comprises the step ofgrowing an epitaxial layer on p-type GaAs;the step of growing anepitaxial layer on a second substrate material comprises the step ofgrowing an epitaxial layer on p-type GaAs; and the steps of depositingfirst and second metals comprise the steps of depositing first andsecond metals selected from the group consisting of Au and Al, the firstand second metals being different.
 29. A method as in claim 22 whereinthe step of growing an epitaxial layer on a first substrate materialcomprises the step of growing an epitaxial layer on n-type GaP;the stepof growing an epitaxial layer on a second substrate material comprisesthe step of growing an epitaxial layer on n-type GaP; and the steps ofdepositing first and second metals comprise the steps of depositingfirst and second metals selected from the group consisting of Cu, Al,Au, Pt, Mg, and Ag, the first and second metals being different.
 30. Amethod as in claim 22 wherein the step of growing an epitaxial layer ona first substrate material comprises the step of growing an epitaxiallayer on n-type Ge;the step of growing an epitaxial layer on a secondsubstrate material comprises the step of growing an epitaxial layer onn-type Ge; and the steps of depositing first and second metals comprisethe steps of depositing first and second metals selected from the groupconsisting of Au and Al, the first and second metals being different.31. A method as in claim 22 wherein the step of growing an epitaxiallayer on a first substrate material comprises the step of growing anepitaxial layer on n-type InP;the step of growing an epitaxial layer ona second substrate material comprises the step of growing an epitaxiallayer on n-type InP; and the steps of depositing first and second metalscomprise the steps of depositing first and second metals selected fromthe group consisting of Au and Ag the first and second metals beingdifferent.
 32. A method as in claim 22 wherein the step of growing anepitaxial layer on a first substrate material comprises the step ofgrowing an epitaxial layer on n-type PbO;the step of growing anepitaxial layer on a second substrate material comprises the step ofgrowing an epitaxial layer on n-type PbO; and the steps of depositingthe first and second metals comprise the steps of depositing first andsecond metals selected from the group consisting of Ag, Bi, Ni, Pb, andIn, the first and second metals being different.
 33. A method as inclaim 22 wherein the step of growing an epitaxial layer on a firstsubstrate material comprises the step of growing an epitaxial layer onn-type Si;the step of growing an epitaxial layer on a second substratematerial comprises the step of growing an epitaxial layer on n-type Si;and the steps of depositing first and second metals comprise the stepsof depositing first and second metals selected from the group consistingof Au, Mo, PtSi and W, the first and second metals being different. 34.A method as in claim 22 wherein the step of growing an epitaxial layeron a first substrate material comprises the step of growing an epitaxiallayer on p-type Si;the step of growing an epitaxial layer on a secondsubstrate material comprises the step of growing an epitaxial layer onp-type Si; and the steps of depositing first and second metals comprisethe steps of depositing first and second metals selected from the groupconsisting of Au and PtSi, the first and second metals being different.35. A method as in claim 22 wherein the step of growing an epitaxiallayer on a first substrate material comprises the step of growing anepitaxial layer on n-type SiC;the step of growing an epitaxial layer ona second substrate material comprises the step of growing an epitaxiallayer on n-type SiC; and the steps of depositing first and second metalscomprise the steps of depositing first and second metals selected fromthe group consisting of Au and A1, the first and second metals beingdifferent.
 36. A method as in claim 22 wherein the step of growing anepitaxial layer on a first substrate material comprises the step ofgrowing an epitaxial layer on n-type SnO2;the step of growing anepitaxial layer on a second substrate material comprises the step ofgrowing an epitaxial layer on n-type SnO2; and the steps of depositingfirst and second metals comprise the steps of depositing first andsecond metals selected from the group consisting of Au, Ag and Cu, thefirst and second metals being different.
 37. A method as in claim 22wherein the step of growing an epitaxial layer on a first substratematerial comprises the step of growing an epitaxial layer on n-typeZnO;the step of growing an epitaxial layer on a second substratematerial comprises the step of growing an epitaxial layer on n-type ZnO;and the steps of depositing first and second metals comprise the stepsof depositing first and second metals selected from the group consistingof Au, Pt, Pd and Ag, the first and second metals being different.
 38. Amethod as in claim 22 wherein the step of growing an epitaxial layer ona first substrate material comprises the step of growing an epitaxiallayer on n-type ZnS;the step of growing an epitaxial layer on a secondsubstrate material comprises the step of growing an epitaxial layer onn-type ZnS; and the steps of depositing first and second metals comprisethe steps of depositing first and second metals selected from the groupconsisting of Au, Pd, Pt, Cu, Ag, In, Al, Ti, and Mg, the first andsecond metals being different.
 39. A method as in claim 22 wherein thestep of growing an epitaxial layer on a first substrate materialcomprises the step of growing an epitaxial layer on n-type ZnSe;the stepof growing an epitaxial layer on a second substrate material comprisesthe step of growing an epitaxial layer on n-type ZnSe; and the steps ofdepositing first and second metals comprise the steps of depositingfirst and second metals selected from the group consisting of Au, Pt, Cuand Mg, the first and second metals being different.
 40. A method as inclaim 22 wherein the step of growing an epitaxial layer on a firstsubstrate material comprises the step of growing an epitaxial layer on asubstrate material selected from the group consisting of n-type AlAs,n-type CdS, n-type CdSe, n-type CdTe, n-type GaAs, p-type GaAs, n-typeGaP, n-type Ge, n-type InP, n-type PbO, n-type Si, p-type Si, n-typeSiC, n-type SnO₂, n-type ZnO, n-type ZnS, and n-type ZnSe.
 41. A methodas in claim 22 wherein the step of growing an epitaxial layer on a firstsubstrate material comprises the step of growing an epitaxial layer on asubstrate material selected from the group consisting of n-type AlAs,n-type CdS, n-type CdSe, n-type CdTe, n-type GaAs, p-type GaAs, n-typeGaP, n-type Ge, n-type InP, n-type PbO, n-type Si, p-type Si, n-typeSiC, n-type SnO₂, n-type ZnO, n-type ZnS, and n-type ZnSe; andthe stepof growing an epitaxial layer on a second substrate material comprisesthe step of growing an epitaxial layer on a substrate material selectedfrom the group consisting of n-type AlAs, n-type CdS, n-type CdSe,n-type CdTe, n-type GaAs, p-type GaAs, n-type GaP, n-type Ge, n-typeInP, n-type PbO, n-type Si, p-type Si, n-type SiC, n-type SnO₂, n-typeZnO, n-type ZnS, and n-type ZnSe.
 42. A method as in claim 22 whereinthe step of growing an epitaxial layer on a first substrate materialcomprises the step of growing an epitaxial layer on n-type ZnO;the stepof growing an epitaxial layer on a second substrate material comprisesthe step of growing an epitaxial layer on n-type ZnO; the step ofdepositing a first metal comprises the step of depositing a metalselected from the group consisting of In and Ti; and the step ofdepositing a second metal consists of the step of depositing Cu.